Bounding pipeline and instruction cache performance
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چکیده
منابع مشابه
Bounding Pipeline and Instruction Cache Performance
Predicting the execution time of code segments in real-time systems is challenging. Most recently designed machines contain pipelines and caches. Pipeline hazards may result in multicycle delays. Instruction or data memory references may not be found in cache and these misses typically require several cycles to resolve. Whether an instruction will stall due to a pipeline hazard or a cache miss ...
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Fast Instruction Cache Performance Evaluation DAVID B. WHALLEY Department of Computer Science B-173, Florida State University, Tallahassee, FL 32306, U.S.A. SUMMARY Cache performance has become a very crucial factor in the overall system performance of machines. Effective analysis of a cache design requires the evaluation of the performance of the cache for typical programs that are to be execu...
متن کاملBounding Worst-Case Data Cache Performance by Using Stack Distance
Worst-case execution time (WCET) analysis is critical for hard real-time systems to ensure that different tasks can meet their respective deadlines. While significant progress has been made for WCET analysis of instruction caches, the data cache timing analysis, especially for setassociative data caches, is rather limited. This paper proposes an approach to safely and tightly bounding data cach...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computers
سال: 1999
ISSN: 0018-9340
DOI: 10.1109/12.743411